The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor Computer On Module definition, targeting applications that require low power, low costs and high performance. The Modules will typically use ARM SOCs similar or the same as those used in many familiar devices such as tablet computers and smart phones. Alternative low power SOCs and CPUs, such as tablet oriented X86 devices and other RISC CPUs may be used as well. The Module power envelope is typically under 6W. The Modules are used as building blocks for portable and stationary embedded systems. The core CPU and support circuits, including DRAM, boot flash, power sequencing, CPU power supplies, GBE and a single channel LVDS display transmitter are concentrated on the Module. The Modules are used with application specific Carrier Boards that implement other features such as audio CODECs, touch controllers, wireless devices, etc. The modular approach allows scalability, fast time to market and upgradability while still maintaining low costs, low power and small physical size. The new global standard under the brand name ‘SMARC’ is based on ULP-COM, the term which up to now was used for Ultra Low Power Computer-on-Modules.
Dimensions
Two Module sizes are defined: 82mm x 50mm and 82mm x 80mm. The Module PCBs have 314 edge fingers that mate with a low profile 314 pin 0.5mm pitch right angle connector (the connector is sometimes identified as a 321 pin connector, but 7 pins are lost to the key).
Signal lines and pin assignments
Signal transmission is carried out via a total of 314 pins. 33 of these are reserved signal lines for power supply and grounding, so that with SMARC a total of 281 signal lines are effectively available. ARM- and SoC-typical energy-saving interfaces, like, for instance, parallel LCD for display connection, mobile industry processor interfaces for cameras, Serial Peripheral Interface (SPI) for general peripheral connection, I2S for audio and I2C are included. Besides these, classical computer interfaces such as USB, SATA and PCI Express are also defined.
Positioning
| / | SMARC | QSevens | ComExpress |
|---|---|---|---|
| Architecture | ARM & SoC | x86 | x86 |
| Typical TDP | 2 Watt (low power) | 12 Watt | 50 Watt (high power) |
| Typical SKU | Freescale ARM, TI ARM | Intel Atom | Intel Atom, Core |
| Specific I/Os | Parallel TFT, LVDS, MIPI CSI camera, MIPI display, I2S, few USB, GPIO, I2C, multiple SPI, serial ports, SDIO | PCIe, LPC, HDA, manu USB | PCIe, PCIe graphics, DDI, LPC, HDA, many USB |
| Connector | 1 x MXM3 | 1 x MXM2 | 1-2 ComExpress connector |
| Pins | 314 | 230 | 220 (type 10) |
| Height | 7.3 mm (w/o heatspreader) | 12 mm | 18 mm |
| Size | 82 mm x 82 mm (full size) 82 mm x 50 mm (short) |
70 mm x 70 mm (Q7) 70 mm x 40 mm (µQ7) |
125 mm x 95 mm (basic) 95 mm x 95 mm (compact) 84 mm x 55 mm (mini) |
| Area | 6560 mm2 4100 mm2 |
4900 mm2 (Q7) 2800 mm2 (µQ7) |
11875 mm2 (basic) 9025 mm2 (compact) 4620 mm2 (mini) |
| Vin | 1.5-5 Volt | 5 Volt | 4-18 Volt |
| Operating System | Linux, Android, WEC | Windos, WEC, Linux, QNX | Windos, Linux, VxWorks |
| Battery Lifetime | Long | Medium | Short |
SMARC 2.0 – The New Specification
The new computer-on-module standard SMARC 2.0 supports up to four digital displays. A new DP++ (Dual-mode DisplayPort) interface to support resolutions up to Ultra HD/4K with 3840 × 2160 pixels was added. It can be used to connect DisplayPort, HDMI and DVI displays. The single-channel LVDS interface in SMARC 1.1 was upgraded to dual-channel LVDS in 2.0. This interface can drive either two low-resolution or one high-resolution display. Depending on which processor is used, the interface can support up to 1920 x 1200 pixels at 60Hz. Since the HDMI/DP interface remains unaltered, developers can connect up to three high resolution digital displays via modern serial display interfaces. Existing carrier boards with single channel LVDS and HDMI can be used with SMARC 2.0 just as before. Furthermore, the number of USB interfaces has been increased significantly. The SMARC 2.0 standard supports up to six USB 2.0 ports and two USB 3.0 interfaces. Also it supports two GbE interfaces including IEEE1588 trigger signals. Four instead of three PCIe lanes are available for platform-specific extensions, which increases the flexibility for individual function extensions. Three of these PCIe lanes are backward compatible with SMARC 1.1. One of the two SPI buses has been upgraded to eSPI/SPI and instead of triple I2S (I2S2 for HDA option) and SPDIF, 1x I2S (for ARM designs) and 1x HDA (for x86 designs) are now supported. What has not been changed is the support of 1x SATA, 12x GPIO, 2x CAN, 1x SDIO (4bit), 4x UART, 1x HDMI, 1x SPI and 4x I2C.
Products
